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WATT SEMICONDUCTORS

Join Our growing team

WATT SEMICONDUCTORS is one of the most innovative network of Independent ASIC Professionals. We want to work with highly talented individuals who want to make a difference. One hundred percent customer satisfaction is our goal.

Kick start your real career now. Be your own boss. Work your own hours. Work directly with your clients without any non-technical middle-management.

If you are an ASIC Design Professional with an zeal for excellence and if you have the necessary qualities and desire to make a difference then please send us your resume.

Currently Open Positions

HIRING NOW
Principal Physical Design Engineer (ICB5)

Responsibilities

The ideal candidate will be responsible for the 3nm high speed physical designs. You will be directly involved in:

  • Floorplanning including multi-power domain, PG planning etc.
  • Physical implementation of blocks and top-level including clock-tree.
  • Physical verification and timing closure for block and chip-level.
  • Static and dynamic IR drop analysis, signal and power EM checks.
  • Methodology & Flow development of Physical Design and Timing Closure.
  • Interfacing with internal and external teams including Design, IP, Library.

Requirements

  • Candidate should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification.
  • Should have excellent problem solving skill to help through congestion resolution and timing closure.
  • Should have experience of formal verification and timing analysis and Eco implementation.
  • Should be able to work independently and help other team members.
  • Should possess ability to learn and adapt to new tools and methodologies.
  • Excellent communication skill is a must.
  • Experience with tools such as Innovus, Calibre, LEC, PrimeTime etc is highly desirable.
  • Full chip tapeout experience based on 3nm technologies is preferred.
  • Experience with TCL and Perl, to achieve higher productivity, is desired

Education and Experience

BE plus 12+ years, or ME plus 10+ years, in deep-sub-micron IC physical designs, or equivalent experience

Apply now
HIRING NOW
Power Distributed Network (PDN) Engineer - Full Time

Responsibilities

  • Apply electrical design expertise to develop Power Distribution Network(PDN) solutions, perform simulation, analysis, and debug.
  • Conduct power integrity analysis for high speed application processor cores and other cores including GPU/Modem
  • Extract PCB and PKG PDN parameters, such as resistance and inductance, using standard industry tools.
  • Perform Lab measurements of PDN in frequency and time domains, including voltage waveform and current waveform.
  • Define bump and ball patterns and decoupling capacitance scheme.
  • Work with system designers, design verification and physical design teams to define, implement, and verify power delivery solutions.

Minimum Qualifications:

  • Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR
  • Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR
  • PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

  • MSc in Electrical Engineering with 5 years of experience in related industry
  • Solid background in package and PCB extraction, analysis flow and SOC floor planning
  • Familiar with industry tools (SIWave, HSPICE, Matlab)
Apply now
HIRING NOW
SOC Electrical Analysis Engineer - Full Time

Responsibilities

  • Develop our Electrical Analysis methodology and infrastructure to enable the verification flow of large SoCs
  • Perform full chip analysis debug and closure of all EA flows, including IR, DVD, EM for signal and power
  • Provide input to full chip floor plan and guidance to the implementation teams throughout the project to enable early convergence and final closure
  • Collaborate with Technology team and CAD partners to drive closure targets and signoff criteria
  • Design and validate Power Distribution Networks optimized for best PPA in specific IPs

Requirements

  • Experience with industry standard EA tools (Apache Redhawk, Cadence Voltus)
  • Understanding of package modeling techniques for full level power analysis
  • Expertise in EA convergence issues associated with high performance designs in advanced process nodes (static and dynamic IR driven timing closure)
  • Strong scripting skills in tcl and python
  • Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
  • Self starter and highly motivated
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules

Education and Experience

  • PhD, Master’s Degree or Bachelor’s Degree in EE, EECS or CS.
Apply now
HIRING NOW
SOC Static Timing Analysis Engineer - Full Time

Responsibilities

  • Block level and/or full chip timing analysis throughout the life cycle of a project, from early investigation to final implementation and tapeout
  • Develop our timing methodology and infrastructure to support the timing flow from RTL synthesis to implementation and timing closure
  • Work with architects and logic designers to generate block and full chip timing constraints
  • Work with system and technology teams to define analysis scenarios and margining strategies
  • Work with system and technology teams to define analysis scenarios and margining strategies
  • Develop a rigorous and comprehensive signoff methodology to guarantee high quality robust silicon
  • Partner with physical design teams to close and sign off the designs

Requirements

  • Hands-on experience in ASIC timing constraints generation and timing closure
  • Expertise and advanced knowledge of industry standard timing EDA tools
  • Deep understanding and experience in timing closure of various functional and test modes
  • Expertise in timing convergence issues associated with deep-sub micron processes (crosstalk delay, noise glitch, POCV, IR-STA)
  • Proficient in scripting languages (csh/bash, TCL and Python)
  • Ability and taste for solving complex problems, efficient written and verbal communication, excellent organization skills
  • Self starter and highly motivated
  • Ability to work cross-functionally with various teams and be productive under aggressive schedules

Education and Experience

  • PhD, Master’s Degree or Bachelor’s Degree in EE, EECS or CS.
Apply now
HIRING NOW
Senior Physical Design Engineer

Responsibilities

  • 7+ years of experience in large VLSI physical design implementation on 28nm and lower technology.
  • Complete understanding of entire Digital backend Physical Design flow from RTL Netlist to GDS2 including floorplanning, power planning, clock tree synthesis, place and route and Timing ECOs, Physical Verification.
  • Signal integrity, OCV, EM/IR, static timing analysis.
  • Understanding of synthesis and timing constraints and timing closure
  • Must have worked as Technical Team Lead or in Project/Design Lead.
  • Successful track record of delivering products to production is a must.
  • Expertise in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tape out issues.
  • Should be a power user of P&R and timing analysis CAD tools from Magma, Cadence or Synopsys
  • Proficiency using Perl, TCL, Scheme, Make scripting is preferred
  • Team player with an enthusiastic, motivated and proactive mindset with excellent communication and personal skills
  • BSEE/MSEE or equivalent with related experience.
Apply now
HIRING NOW
ASIC Implementation Engineer

Job Responsibilities may include:

  • Customer communication
  • Floor planning chips and blocks
  • Routing
  • Timing, both mission mode and test modes
  • Integration of memories, SerDes, and I/O
  • Work effectively with cross functional teams
  • Integration of test and clocking structures
  • Design of complex standard cell custom blocks.
  • Understanding of design tradeoffs for power, area, and speed.
  • Physical verification to ensure error free artwork/mask release.

Minimum Qualifications:

  • Bachelor’s Degree in Electrical Engineering or Computer Engineering + 2 yrs experience
  • Master’s Degree in Electrical Engineering or Computer Engineering
  • Self-motivated with the capability to work independently and as a member of a team to deliver quality designs
  • Possess outstanding critical thinking, and communication skills
  • Should be a power user of P&R and timing analysis using Cadence Stylus or Synopsys Fusion Compiler
  • Proficiency using Perl, TCL is must have and Python scripting is preferred
  • Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tape out issues.
Apply now

Registration Details

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We're your Power Experts for PDN Sign-off and RTL to GDSII flows