We will refer to Synopsys Fusion Compiler commands for this example.
Key Steps Explained<\/strong><\/p>\n\n\n\n
- \n
- Layer Selection<\/strong>: Use upper metals (e.g.,
M4\/M5<\/code>) for feedthroughs to avoid block-level routing.<\/li>\n\n\n\n- Blockage Alignment<\/strong>: Ensure feedthroughs don\u2019t overlap macros or power straps.<\/li>\n\n\n\n
- Hierarchical Flow<\/strong>: Save feedthroughs in DEF for top-level integration.<\/li>\n<\/ul>\n\n\n\n
Port Creation<\/strong>:<\/p>\n\n\n\n
- \n
create_port<\/code> adds feedthrough ports at the boundaries ofBlock_A<\/code> andBlock_B<\/code>.<\/li>\n\n\n\n-direction inout<\/strong><\/code> allows bidirectional signal flow (adjust if unidirectional).<\/li>\n<\/ul>\n\n\n\nNet Creation<\/strong>:<\/p>\n\n\n\n
- \n
create_net<\/code> defines the feedthrough net and connects ports across blocks.<\/li>\n<\/ul>\n\n\n\nBuffering<\/strong>:<\/p>\n\n\n\n
- \n
insert_buffer<\/code> prevents signal degradation over long distances (critical for timing).<\/li>\n<\/ul>\n\n\n\nHandling Power State Conflicts<\/strong><\/p>\n\n\n\n
<\/p>\n\n\n\n
Routing Constraints<\/strong>:<\/p>\n\n\n\n
- \n
set_feedthrough_strategy<\/code> reserves metal layers (e.g.,M4<\/code>) to avoid congestion.<\/li>\n<\/ul>\n\n\n\nLegalization<\/strong>:<\/p>\n\n\n\n
- \n
- Ensures feedthroughs don\u2019t violate placement\/routing rules.<\/li>\n<\/ul>\n\n\n\n
Verification<\/strong>:<\/p>\n\n\n\n
report_net<\/code> andcheck_connectivity<\/code> validate the feedthrough path.<\/p>\n\n\n\n<\/p>\n\n\n\n
<\/p>\n\n\n\n
![\"\"](\"https:\/\/wattsemi.com\/wp-content\/uploads\/2025\/07\/image.png\")
<\/figure>\n\n\n\n
<\/p>\n\n\n\n
\n\n\n\nHere\u2019s a TCL script<\/strong> for Synopsys Fusion Compiler<\/strong> to insert feedthrough ports and nets between
Block_A<\/code> andBlock_B<\/code> during floorplanning, ensuring clean signal routing across hierarchical boundaries:<\/p>\n\n\n\n1. Script to Create Feedthrough Ports and Nets<\/strong><\/h3>\n\n\n\n
#!\/usr\/bin\/env tclsh\n\n# Load the design and floorplan\nread_db -technology \"tech.tf\"\nread_verilog \"design.v\"\nlink_design -top \"TOP\"\n\n# Define block boundaries (adjust coordinates as needed)\nset blockA_bbox {100 100 300 400} ;# Block_A: x1 y1 x2 y2\nset blockB_bbox {500 100 700 400} ;# Block_B: x1 y1 x2 y2\n\n# Create feedthrough ports on Block_A and Block_B\ncreate_port -direction inout -bbox $blockA_bbox FT_AtoB\ncreate_port -direction inout -bbox $blockB_bbox FT_BtoA\n\n# Create feedthrough net and connect ports\ncreate_net -net_type feedthrough FT_NET\nconnect_net -net FT_NET -ports {FT_AtoB FT_BtoA}\n\n# Add buffers to prevent signal degradation\ninsert_buffer -net FT_NET -cell BUF_X2 -location [expr [lindex $blockA_bbox 0] + 50] [expr [lindex $blockA_bbox 1] + 50]\n\n# Reserve routing tracks for feedthrough (e.g., Metal4)\nset_feedthrough_strategy -nets FT_NET -layers {M4} -width 0.2 -spacing 0.5\n\n# Legalize placement to avoid DRCs\nlegalize_placement -nets FT_NET\n\n# Verify feedthrough connectivity\nreport_net -nets FT_NET -verbose\ncheck_connectivity -nets FT_NET\n\n# Save floorplan changes\nwrite_def -output \"feedthrough_def.def\"\nwrite_verilog -output \"feedthrough_netlist.v\"<\/em><\/code><\/pre>\n\n\n\n
\n\n\n\n
2. Advanced Enhancements<\/strong><\/h3>\n\n\n\nA. Timing-Driven Feedthroughs<\/strong><\/h4>\n\n\n\n
# Set max delay constraint for feedthrough net\nset_max_delay -from [get_ports FT_AtoB] -to [get_ports FT_BtoA] 1.5 -datapath_only\n<\/em>\n# Optimize feedthrough path\npsynopt -nets FT_NET -effort high<\/em><\/code><\/pre>\n\n\n\nB. Power-Aware Routing<\/strong><\/h4>\n\n\n\n
# Shield feedthrough to reduce noise\nset_feedthrough_strategy -nets FT_NET -shield_net VSS -shield_width 0.1<\/em><\/code><\/pre>\n\n\n\nC. Automated Feedthrough Insertion<\/strong><\/h4>\n\n\n\n
# Loop to create multiple feedthroughs\nforeach net {data1 data2 clk} {\n create_port -direction inout -bbox $blockA_bbox FT_${net}_A\n create_port -direction inout -bbox $blockB_bbox FT_${net}_B\n create_net -net_type feedthrough FT_${net}\n connect_net -net FT_${net} -ports [list FT_${net}_A FT_${net}_B]\n}<\/em><\/code><\/pre>\n\n\n\n
\n\n\n\n3. Verification Commands<\/strong><\/h3>\n\n\n\n
# Check feedthrough timing\nreport_timing -from FT_AtoB -to FT_BtoA\n\n# Verify DRCs\nverify_drc -nets FT_NET\n\n# Report congestion near feedthroughs\nreport_congestion -area [list $blockA_bbox $blockB_bbox]<\/em><\/code><\/pre>\n\n\n\nVerification Commands<\/strong> for AON FT buffering though collapsible domains:<\/h6>\n\n\n\n
# Check AON buffer placement
report_power_domain -cells [get_cells -filter “ref_name=~BUF_X1_AON*”]
# Verify domain crossings
check_power_domains -nets $feedthrough_nets -verbose
# Timing checks (AON buffers should not be gated)
report_timing -from [get_pins -of [get_cells -filter “ref_name==BUF_X1_AON”]*\/A] \\
-to [get_pins -of [get_cells -filter “ref_name==BUF_X1_AON”]*\/Z]<\/em><\/p>\n\n\n\n
\n\n\n\n4. Key Considerations<\/strong><\/h3>\n\n\n\n
Library Cells<\/strong>: Use AON-specific buffers (marked
-always_on<\/code> in the library).<\/p>\n\n\n\nPlacement<\/strong>: Keep AON buffers near domain boundaries to minimize wire length.<\/p>\n\n\n\n
Routing<\/strong>: Use non-collapsible power rails (e.g.,
VDD_AON<\/code>) for AON buffers.<\/p>\n\n\n\n
Q<\/strong>: “How do you ensure feedthroughs don\u2019t worsen congestion?”<\/em>
Reserve dedicated metal layers (e.g.,M4<\/code>) for feedthroughs usingset_feedthrough_strategy<\/code>, analyze congestion withreport_congestion<\/code>, and avoid high-density regions. <\/em>
If needed, I adjust placement blockages.<\/em><\/p>\n\n\n\nQ<\/strong>: “What if the feedthrough net fails timing?”<\/em><\/p>\n\n\n\n
“Insert buffers (
BUF_X2<\/code>) andset_max_delay<\/code> constraints. For critical nets, use wider metal layers or shield with VSS to reduce crosstalk.”<\/em><\/p>\n\n\n\nQ<\/strong>: “What if the AON buffer fails timing?”<\/em><\/p>\n\n\n\n
“Size up the buffer (
BUF_X2_AON<\/code>) or adjust placement to reduce wire delay. For critical paths, useset_max_delay<\/code> to prioritize domain-crossing nets.”<\/em><\/p>\n\n\n\nQ<\/strong>: “How do you ensure feedthrough buffers stay always-on?”<\/em><\/p>\n\n\n\n
“Tag them with
-power_domain PD_AON<\/code> during insertion and verify viareport_power_domain<\/code>. The UPF file enforces-always_on<\/code> forPD_AON<\/code>.”<\/em><\/p>\n\n\n\n
\n\n\n\nAON Buffer Insertion Strategy<\/strong> for inserting feedthrough signals through a collapsible domain.<\/h3>\n\n\n\n
A. Identify Feedthrough Signals Crossing Domains<\/strong><\/h4>\n\n\n\n
# Get all feedthrough nets between Block_A (collapsible) and Block_B (AON)\nset feedthrough_nets [get_nets -of [get_pins -filter \"full_name=~Block_A*||full_name=~Block_B*\"]]<\/em><\/code><\/pre>\n\n\n\nB. Insert AON Buffers for Domain Crossing<\/strong><\/h4>\n\n\n\n
foreach net $feedthrough_nets {\n # Check if net crosses power domains (collapsible \u2194 AON)\n set driver_pd [get_power_domain -of [get_drivers $net]]\n set load_pd [get_power_domain -of [get_loads $net]]\n\n if {($driver_pd != $load_pd) && ($driver_pd == \"PD_CPU\" || $load_pd == \"PD_CPU\")} {\n # Insert AON buffer (ensure it's in PD_AON)\n set buf_cell \"BUF_X1_AON\" ;# Library cell with AON attribute\n set buf_loc [get_location -median $net] ;# Place near domain boundary\n\n insert_buffer -net $net -cell $buf_cell -location $buf_loc \\\n -power_domain PD_AON -placement_guide AON_REGION\n\n # Connect buffer output to AON domain\n connect_net -net $net -ports [get_pins -of [get_cells -filter \"ref_name==$buf_cell\"]]\n }\n}<\/em><\/code><\/pre>\n\n\n\nC. Define Placement Guides for AON Buffers<\/strong><\/h4>\n\n\n\n
# Create an AON buffer region near the domain boundary\ncreate_placement_blockage -name AON_REGION -bbox {x1 y1 x2 y2} -type partial\nset_app_options -name plan.pgroute.power_domain_aware -value true<\/em><\/code><\/pre>\n\n\n\n
\n\n\n\nHandling Power State Conflicts<\/strong><\/h3>\n\n\n\n
A. Isolation Cell Insertion (Optional)<\/strong><\/h4>\n\n\n\n
If feedthrough signals need isolation when the collapsible domain is off:<\/p>\n\n\n\n
set_isolation -domain PD_CPU -isolation_power_net VDD_AON \\\n -isolation_ground_net VSS -clamp_value 0 \\\n -applies_to outputs<\/em><\/code><\/pre>\n\n\n\nB. Level Shifter Insertion (Voltage Crossing)<\/strong><\/h4>\n\n\n\n
If domains operate at different voltages:<\/p>\n\n\n\n
insert_level_shifter -net $net -from PD_CPU -to PD_AON \\\n -location $buf_loc -cell LVL_SHIFT_AON<\/em><\/code><\/pre>\n\n\n\n
\n\n\n\n
\n\n\n\nUPF\/CPF Constraints Example<\/strong><\/h3>\n\n\n\n
Ensure UPF\/CPF defines
PD_AON<\/code> as always-on:<\/p>\n\n\n\ncreate_power_domain PD_AON -elements [list BUF_X1_AON*] -always_on\ncreate_power_domain PD_CPU -shutoff_condition {!PWR_EN}<\/em><\/code><\/pre>\n\n\n\n
\n\n\n\n<\/h3>\n\n\n\n
![\"\"](\"https:\/\/wattsemi.com\/wp-content\/uploads\/2025\/07\/image.jpeg\")
<\/figure>\n","protected":false},"excerpt":{"rendered":"ASIC Low Power Physical Design: Inserting FeedThroughs: Ever wonder how complex Feedthrough signals are routed between two Hard Macros when propagating through collapsible blocks, while navigating the challenges of meeting STA timing, routing congestion and UPF constrains with isolation cells? Here\u2019s a simplified and structured approach on the basics of how to handle domain crossings […]<\/p>\n","protected":false},"author":2,"featured_media":26442,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"postBodyCss":"","postBodyMargin":[],"postBodyPadding":[],"postBodyBackground":{"backgroundType":"classic","gradient":""},"footnotes":""},"categories":[40],"tags":[],"class_list":["post-26432","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-technology"],"_links":{"self":[{"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/posts\/26432","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/wattsemi.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=26432"}],"version-history":[{"count":7,"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/posts\/26432\/revisions"}],"predecessor-version":[{"id":26445,"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/posts\/26432\/revisions\/26445"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/wattsemi.com\/index.php?rest_route=\/wp\/v2\/media\/26442"}],"wp:attachment":[{"href":"https:\/\/wattsemi.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=26432"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/wattsemi.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=26432"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/wattsemi.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=26432"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
- Ensures feedthroughs don\u2019t violate placement\/routing rules.<\/li>\n<\/ul>\n\n\n\n
- Blockage Alignment<\/strong>: Ensure feedthroughs don\u2019t overlap macros or power straps.<\/li>\n\n\n\n