WATT SEMI

Turnkey solutions from RTL to GDS2

The need for excellence in implementation of ASIC
Physical Design

With the technology shrinking from 0.18µm used 7 years ago to 35ηm today and increasing gate counts and ultra-fast complex clocking structures , the need for efficient Physical Design from RTL to GDS2 has grown steadily over the last decade.

A well implemented and optimized physical design can help with:

  • Major cost savings due to reduction in die-area during synthesis, floorplan and optimizations.
  • Result in lower power consumption achieved with:
    ‣ Improved CTS with optimizations, gating and correct by construction.
    ‣ Leakage analysis and optimizations with use of Multi-VT libraries.
    ‣ Use of power domains and voltage islands.
  • Improved yield due to better analysis of Design for Manufacturability (DFM),
  • Improved product life with analysis of Signal Integrity, EM and IR drop,
  • Better predictability in failures with On-Chip-Variations enabled during Static Timing Analysis across multiple corners and modes.
  • Faster time-to-market with cleaner routing, fewer iterations and DRC/LVS violations to fix.

Challenges:

Frequent revisions for adding product features, functionality enhancements and companies going fabless, the time-to-market is critical. It is determined by several factors including the methodology and flows used, engineering teamwork and skills, as well as a wide choice of EDA tools and the route chosen from RTL to GDS2.

Our dedicated team helps to mitigate these risks and provide fast, efficient and quality data.

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